Ushenina I.V. 1
Elizarov V.N. 1
Varnavskiy V.A. 1
1 Penza State Technological Academy
Multiplier-free distributed digital filter with finite impulse response is presented. The main characteristics of the filter are: the possibility of adjusting such filter’s parameters as order, input and output signals capacity, coefficients; low latency in comparison with classical structure; availability for implementation on the base of programmable resources of the FPGA. There is two’s complement, fixed-point number representation in a filter. Possibilities of the filter implementation on the base of FPGA are analyzed. It is shown that filter consists of registers, RAM memory, adder, controllable invertor, finite state machine, counter, combinatorial logic. The dependencies of the filter’s elements and buses capacities, control signals durations, etc. from it’s given parameters are obtained. The results of the functional simulation of the filter are shown. The problems concerned with restrictions of using RAM-based digital filters are considered.