Popov S.D. 1
Opadchiy Y.F. 1
1 «MATI» – Russian State University of Aviation Technology n.a. K.E. Tsiolkovsky
In this article, we have considered the optimization of the tabular method for the computation of the values of the exponential function. The main drawback of tabular method lies in the fact that, in practice, the amount of information that must be stored in the table is too large, which implies high hardware costs. The proposed method consists in splitting of the binary representation of the argument, which allows to reduce the problem to the readings of several small tables, that contain 4 lines. The proposed method considered in detail by the example of calculation of the value of the exponential function. We have carried out a comparison of the proposed method and algorithm, built-in in the CAD Altera Quartus II, on the FPGA Altera Stratix III. With the limited range of changes of the argument, the proposed algorithm has a clear advantage, as the cost of hardware resources of the FPGA, and so on speed.